Discussion:
vex: r3371 - in /trunk: priv/main_main.c pub/libvex.h
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s***@valgrind.org
2017-05-16 06:26:48 UTC
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Author: sewardj
Date: Tue May 16 07:26:48 2017
New Revision: 3371

Log:
arm64-linux: detect Cavium CPUs (implementer = 0x43) and enable the
fallback LLSC implementation in that case. Pertains to bug #369459.
(VEX side changes)

Modified:
trunk/priv/main_main.c
trunk/pub/libvex.h

Modified: trunk/priv/main_main.c
==============================================================================
--- trunk/priv/main_main.c (original)
+++ trunk/priv/main_main.c Tue May 16 07:26:48 2017
@@ -1468,6 +1468,7 @@
vai->ppc_dcbzl_szB = 0;
vai->arm64_dMinLine_lg2_szB = 0;
vai->arm64_iMinLine_lg2_szB = 0;
+ vai->arm64_requires_fallback_LLSC = False;
vai->hwcache_info.num_levels = 0;
vai->hwcache_info.num_caches = 0;
vai->hwcache_info.caches = NULL;

Modified: trunk/pub/libvex.h
==============================================================================
--- trunk/pub/libvex.h (original)
+++ trunk/pub/libvex.h Tue May 16 07:26:48 2017
@@ -323,6 +323,9 @@
line size of 64 bytes would be encoded here as 6. */
UInt arm64_dMinLine_lg2_szB;
UInt arm64_iMinLine_lg2_szB;
+ /* ARM64: does the host require us to use the fallback LLSC
+ implementation? */
+ Bool arm64_requires_fallback_LLSC;
}
VexArchInfo;

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