Discussion:
vex: r3349 - /branches/VEX_JIT_HACKS/priv/
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s***@valgrind.org
2017-04-16 20:36:48 UTC
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Author: iraisr
Date: Sun Apr 16 21:36:48 2017
New Revision: 3349

Log:
Extend host instruction interface with HInstrSB, HInstrVec and HInstrIfThenElse.

Modified:
branches/VEX_JIT_HACKS/priv/host_amd64_defs.h
branches/VEX_JIT_HACKS/priv/host_arm64_defs.h
branches/VEX_JIT_HACKS/priv/host_arm_defs.h
branches/VEX_JIT_HACKS/priv/host_generic_regs.c
branches/VEX_JIT_HACKS/priv/host_generic_regs.h
branches/VEX_JIT_HACKS/priv/host_mips_defs.h
branches/VEX_JIT_HACKS/priv/host_ppc_defs.h
branches/VEX_JIT_HACKS/priv/host_s390_defs.h
branches/VEX_JIT_HACKS/priv/host_tilegx_defs.h
branches/VEX_JIT_HACKS/priv/host_x86_defs.c
branches/VEX_JIT_HACKS/priv/host_x86_defs.h
branches/VEX_JIT_HACKS/priv/host_x86_isel.c
branches/VEX_JIT_HACKS/priv/main_main.c

Modified: branches/VEX_JIT_HACKS/priv/host_amd64_defs.h
==============================================================================
--- branches/VEX_JIT_HACKS/priv/host_amd64_defs.h (original)
+++ branches/VEX_JIT_HACKS/priv/host_amd64_defs.h Sun Apr 16 21:36:48 2017
@@ -804,7 +804,7 @@

extern const RRegUniverse* getRRegUniverse_AMD64 ( void );

-extern HInstrArray* iselSB_AMD64 ( const IRSB*,
+extern HInstrSB* iselSB_AMD64 ( const IRSB*,
VexArch,
const VexArchInfo*,
const VexAbiInfo*,

Modified: branches/VEX_JIT_HACKS/priv/host_arm64_defs.h
==============================================================================
--- branches/VEX_JIT_HACKS/priv/host_arm64_defs.h (original)
+++ branches/VEX_JIT_HACKS/priv/host_arm64_defs.h Sun Apr 16 21:36:48 2017
@@ -982,7 +982,7 @@

extern const RRegUniverse* getRRegUniverse_ARM64 ( void );

-extern HInstrArray* iselSB_ARM64 ( const IRSB*,
+extern HInstrSB* iselSB_ARM64 ( const IRSB*,
VexArch,
const VexArchInfo*,
const VexAbiInfo*,

Modified: branches/VEX_JIT_HACKS/priv/host_arm_defs.h
==============================================================================
--- branches/VEX_JIT_HACKS/priv/host_arm_defs.h (original)
+++ branches/VEX_JIT_HACKS/priv/host_arm_defs.h Sun Apr 16 21:36:48 2017
@@ -1073,7 +1073,7 @@

extern const RRegUniverse* getRRegUniverse_ARM ( void );

-extern HInstrArray* iselSB_ARM ( const IRSB*,
+extern HInstrSB* iselSB_ARM ( const IRSB*,
VexArch,
const VexArchInfo*,
const VexAbiInfo*,

Modified: branches/VEX_JIT_HACKS/priv/host_generic_regs.c
==============================================================================
--- branches/VEX_JIT_HACKS/priv/host_generic_regs.c (original)
+++ branches/VEX_JIT_HACKS/priv/host_generic_regs.c Sun Apr 16 21:36:48 2017
@@ -282,28 +282,70 @@
/*--- Abstract instructions ---*/
/*---------------------------------------------------------*/

-HInstrArray* newHInstrArray ( void )
+HInstrVec* newHInstrVec(void)
{
- HInstrArray* ha = LibVEX_Alloc_inline(sizeof(HInstrArray));
- ha->arr_size = 4;
- ha->arr_used = 0;
- ha->arr = LibVEX_Alloc_inline(ha->arr_size * sizeof(HInstr*));
- ha->n_vregs = 0;
- return ha;
+ HInstrVec* hv = LibVEX_Alloc_inline(sizeof(HInstrVec));
+ hv->insns_size = 4;
+ hv->insns_used = 0;
+ hv->insns = LibVEX_Alloc_inline(hv->insns_size * sizeof(HInstr*));
+ return hv;
}

__attribute__((noinline))
-void addHInstr_SLOW ( HInstrArray* ha, HInstr* instr )
+void addHInstr_SLOW(HInstrVec* hv, HInstr* instr)
{
- vassert(ha->arr_used == ha->arr_size);
- Int i;
- HInstr** arr2 = LibVEX_Alloc_inline(ha->arr_size * 2 * sizeof(HInstr*));
- for (i = 0; i < ha->arr_size; i++) {
- arr2[i] = ha->arr[i];
+ vassert(hv->insns_used == hv->insns_size);
+ HInstr** insns2 = LibVEX_Alloc_inline(hv->insns_size * 2 * sizeof(HInstr*));
+ for (UInt i = 0; i < hv->insns_size; i++) {
+ insns2[i] = hv->insns[i];
}
- ha->arr_size *= 2;
- ha->arr = arr2;
- addHInstr(ha, instr);
+ hv->insns_size *= 2;
+ hv->insns = insns2;
+ addHInstr(hv, instr);
+}
+
+static void print_depth(UInt depth) {
+ for (UInt i = 0; i < depth; i++) {
+ vex_printf(" ");
+ }
+}
+
+static void ppHInstrVec(const HInstrVec* code,
+ HInstrIfThenElse* (*isIfThenElse)(const HInstr*),
+ void (*ppInstr)(const HInstr*, Bool),
+ Bool mode64, UInt depth, UInt *insn_num)
+{
+ for (UInt i = 0; i < code->insns_used; i++) {
+ const HInstr* instr = code->insns[i];
+ const HInstrIfThenElse* hite = isIfThenElse(instr);
+ if (UNLIKELY(hite != NULL)) {
+ ppHInstrVec(hite->fallThrough, isIfThenElse, ppInstr, mode64,
+ depth + 1, insn_num);
+ ppHInstrVec(hite->outOfLine, isIfThenElse, ppInstr, mode64,
+ depth + 1, insn_num);
+ } else {
+ vex_printf("%3u ", (*insn_num)++);
+ print_depth(depth);
+ ppInstr(instr, mode64);
+ vex_printf("\n");
+ }
+ }
+}
+
+HInstrSB* newHInstrSB(void)
+{
+ HInstrSB* hsb = LibVEX_Alloc_inline(sizeof(HInstrSB));
+ hsb->insns = newHInstrVec();
+ hsb->n_vregs = 0;
+ return hsb;
+}
+
+void ppHInstrSB(const HInstrSB* code,
+ HInstrIfThenElse* (*isIfThenElse)(const HInstr*),
+ void (*ppInstr)(const HInstr*, Bool), Bool mode64)
+{
+ UInt insn_num = 0;
+ ppHInstrVec(code->insns, isIfThenElse, ppInstr, mode64, 0, &insn_num);
}



Modified: branches/VEX_JIT_HACKS/priv/host_generic_regs.h
==============================================================================
--- branches/VEX_JIT_HACKS/priv/host_generic_regs.h (original)
+++ branches/VEX_JIT_HACKS/priv/host_generic_regs.h Sun Apr 16 21:36:48 2017
@@ -338,42 +338,66 @@
/* A type is needed to refer to pointers to instructions of any
target. Defining it like this means that HInstr* can stand in for
X86Instr*, ArmInstr*, etc. */
-
typedef void HInstr;


-/* An expandable array of HInstr*'s. Handy for insn selection and
- register allocation. n_vregs indicates the number of virtual
- registers mentioned in the code, something that reg-alloc needs to
- know. These are required to be numbered 0 .. n_vregs-1.
-*/
+/* An expandable vector of HInstr*'s. Handy for insn selection and
+ register allocation. */
typedef
struct {
- HInstr** arr;
- Int arr_size;
- Int arr_used;
- Int n_vregs;
+ HInstr** insns;
+ UInt insns_size;
+ UInt insns_used;
}
- HInstrArray;
+ HInstrVec;

-extern HInstrArray* newHInstrArray ( void );
+extern HInstrVec* newHInstrVec(void);

/* Never call this directly. It's the slow and incomplete path for
addHInstr. */
__attribute__((noinline))
-extern void addHInstr_SLOW ( HInstrArray*, HInstr* );
+extern void addHInstr_SLOW(HInstrVec*, HInstr*);

-static inline void addHInstr ( HInstrArray* ha, HInstr* instr )
+static inline void addHInstr(HInstrVec* ha, HInstr* instr)
{
- if (LIKELY(ha->arr_used < ha->arr_size)) {
- ha->arr[ha->arr_used] = instr;
- ha->arr_used++;
+ if (LIKELY(ha->insns_used < ha->insns_size)) {
+ ha->insns[ha->insns_used] = instr;
+ ha->insns_used++;
} else {
addHInstr_SLOW(ha, instr);
}
}


+/* Represents two alternative code paths:
+ - one more likely taken (hot path)
+ - one not so likely taken (cold path) */
+typedef
+ struct {
+ // HCondCode ccOOL; // TODO-JIT: condition code for the OOL branch
+ HInstrVec* fallThrough; // generated from the likely-taken IR
+ HInstrVec* outOfLine; // generated from likely-not-taken IR
+ }
+ HInstrIfThenElse;
+
+
+/* Code block of HInstr's.
+ n_vregs indicates the number of virtual registers mentioned in the code,
+ something that reg-alloc needs to know. These are required to be
+ numbered 0 .. n_vregs-1. */
+typedef
+ struct {
+ HInstrVec* insns;
+ UInt n_vregs;
+ }
+ HInstrSB;
+
+extern HInstrSB* newHInstrSB(void);
+extern void ppHInstrSB(const HInstrSB* code,
+ HInstrIfThenElse* (*isIfThenElse)(const HInstr*),
+ void (*ppInstr)(const HInstr*, Bool), Bool mode64);
+
+
/*---------------------------------------------------------*/
/*--- C-Call return-location descriptions ---*/
/*---------------------------------------------------------*/
@@ -443,10 +467,10 @@
/*---------------------------------------------------------*/

extern
-HInstrArray* doRegisterAllocation (
+HInstrSB* doRegisterAllocation (

/* Incoming virtual-registerised code. */
- HInstrArray* instrs_in,
+ HInstrSB* sb_in,

/* The real-register universe to use. This contains facts about
real registers, one of which is the set of registers available
@@ -463,6 +487,10 @@
/* Apply a reg-reg mapping to an insn. */
void (*mapRegs) (HRegRemap*, HInstr*, Bool),

+ /* Is this instruction actually HInstrIfThenElse? Returns pointer to
+ HInstrIfThenElse if yes, NULL otherwise. */
+ HInstrIfThenElse* (*isIfThenElse) (const HInstr*),
+
/* Return insn(s) to spill/restore a real reg to a spill slot
offset. And optionally a function to do direct reloads. */
void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool ),

Modified: branches/VEX_JIT_HACKS/priv/host_mips_defs.h
==============================================================================
--- branches/VEX_JIT_HACKS/priv/host_mips_defs.h (original)
+++ branches/VEX_JIT_HACKS/priv/host_mips_defs.h Sun Apr 16 21:36:48 2017
@@ -703,7 +703,7 @@

extern const RRegUniverse* getRRegUniverse_MIPS ( Bool mode64 );

-extern HInstrArray *iselSB_MIPS ( const IRSB*,
+extern HInstrSB *iselSB_MIPS ( const IRSB*,
VexArch,
const VexArchInfo*,
const VexAbiInfo*,

Modified: branches/VEX_JIT_HACKS/priv/host_ppc_defs.h
==============================================================================
--- branches/VEX_JIT_HACKS/priv/host_ppc_defs.h (original)
+++ branches/VEX_JIT_HACKS/priv/host_ppc_defs.h Sun Apr 16 21:36:48 2017
@@ -1218,7 +1218,7 @@

extern const RRegUniverse* getRRegUniverse_PPC ( Bool mode64 );

-extern HInstrArray* iselSB_PPC ( const IRSB*,
+extern HInstrSB* iselSB_PPC ( const IRSB*,
VexArch,
const VexArchInfo*,
const VexAbiInfo*,

Modified: branches/VEX_JIT_HACKS/priv/host_s390_defs.h
==============================================================================
--- branches/VEX_JIT_HACKS/priv/host_s390_defs.h (original)
+++ branches/VEX_JIT_HACKS/priv/host_s390_defs.h Sun Apr 16 21:36:48 2017
@@ -749,7 +749,7 @@
const RRegUniverse *getRRegUniverse_S390( void );
void genSpill_S390 ( HInstr **, HInstr **, HReg , Int , Bool );
void genReload_S390 ( HInstr **, HInstr **, HReg , Int , Bool );
-HInstrArray *iselSB_S390 ( const IRSB *, VexArch, const VexArchInfo *,
+HInstrSB *iselSB_S390 ( const IRSB *, VexArch, const VexArchInfo *,
const VexAbiInfo *, Int, Int, Bool, Bool, Addr);

/* Return the number of bytes of code needed for an event check */

Modified: branches/VEX_JIT_HACKS/priv/host_tilegx_defs.h
==============================================================================
--- branches/VEX_JIT_HACKS/priv/host_tilegx_defs.h (original)
+++ branches/VEX_JIT_HACKS/priv/host_tilegx_defs.h Sun Apr 16 21:36:48 2017
@@ -532,10 +532,10 @@

extern const RRegUniverse* getRRegUniverse_TILEGX ( void );

-extern HInstrArray *iselSB_TILEGX ( const IRSB*, VexArch,
- const VexArchInfo*,
- const VexAbiInfo*,
- Int, Int, Bool, Bool, Addr);
+extern HInstrSB *iselSB_TILEGX ( const IRSB*, VexArch,
+ const VexArchInfo*,
+ const VexAbiInfo*,
+ Int, Int, Bool, Bool, Addr);
extern const HChar *showTILEGXCondCode ( TILEGXCondCode cond );
extern Int evCheckSzB_TILEGX (void);
extern VexInvalRange chainXDirect_TILEGX ( VexEndness endness_host,

Modified: branches/VEX_JIT_HACKS/priv/host_x86_defs.c
==============================================================================
--- branches/VEX_JIT_HACKS/priv/host_x86_defs.c (original)
+++ branches/VEX_JIT_HACKS/priv/host_x86_defs.c Sun Apr 16 21:36:48 2017
@@ -1697,6 +1697,13 @@
return False;
}

+extern HInstrIfThenElse* isIfThenElse_X86Instr(X86Instr* i)
+{
+ if (UNLIKELY(i->tag == Xin_IfThenElse)) {
+ return i->Xin.IfThenElse.hite;
+ }
+ return NULL;
+}

/* Generate x86 spill/reload instructions under the direction of the
register allocator. Note it's critical these don't write the

Modified: branches/VEX_JIT_HACKS/priv/host_x86_defs.h
==============================================================================
--- branches/VEX_JIT_HACKS/priv/host_x86_defs.h (original)
+++ branches/VEX_JIT_HACKS/priv/host_x86_defs.h Sun Apr 16 21:36:48 2017
@@ -388,7 +388,8 @@
Xin_SseCMov, /* SSE conditional move */
Xin_SseShuf, /* SSE2 shuffle (pshufd) */
Xin_EvCheck, /* Event check */
- Xin_ProfInc /* 64-bit profile counter increment */
+ Xin_ProfInc, /* 64-bit profile counter increment */
+ Xin_IfThenElse /* HInstrIfThenElse */
}
X86InstrTag;

@@ -652,6 +653,9 @@
installed later, post-translation, by patching it in,
as it is not known at translation time. */
} ProfInc;
+ struct {
+ HInstrIfThenElse* hite;
+ } IfThenElse;

} Xin;
}
@@ -717,6 +721,7 @@
extern void getRegUsage_X86Instr ( HRegUsage*, const X86Instr*, Bool );
extern void mapRegs_X86Instr ( HRegRemap*, X86Instr*, Bool );
extern Bool isMove_X86Instr ( const X86Instr*, HReg*, HReg* );
+extern HInstrIfThenElse* isIfThenElse_X86Instr(X86Instr*);
extern Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc,
UChar* buf, Int nbuf, const X86Instr* i,
Bool mode64,
@@ -735,7 +740,7 @@

extern const RRegUniverse* getRRegUniverse_X86 ( void );

-extern HInstrArray* iselSB_X86 ( const IRSB*,
+extern HInstrSB* iselSB_X86 ( const IRSB*,
VexArch,
const VexArchInfo*,
const VexAbiInfo*,

Modified: branches/VEX_JIT_HACKS/priv/host_x86_isel.c
==============================================================================
--- branches/VEX_JIT_HACKS/priv/host_x86_isel.c (original)
+++ branches/VEX_JIT_HACKS/priv/host_x86_isel.c Sun Apr 16 21:36:48 2017
@@ -185,7 +185,7 @@
Addr32 max_ga;

/* These are modified as we go along. */
- HInstrArray* code;
+ HInstrSB* code;
Int vreg_ctr;
}
ISelEnv;
@@ -209,7 +209,7 @@

static void addInstr ( ISelEnv* env, X86Instr* instr )
{
- addHInstr(env->code, instr);
+ addHInstr(env->code->insns, instr);
if (vex_traceflags & VEX_TRACE_VCODE) {
ppX86Instr(instr, False);
vex_printf("\n");
@@ -4420,7 +4420,7 @@

/* Translate an entire SB to x86 code. */

-HInstrArray* iselSB_X86 ( const IRSB* bb,
+HInstrSB* iselSB_X86 ( const IRSB* bb,
VexArch arch_host,
const VexArchInfo* archinfo_host,
const VexAbiInfo* vbi/*UNUSED*/,
@@ -4453,7 +4453,7 @@
env->vreg_ctr = 0;

/* Set up output code array. */
- env->code = newHInstrArray();
+ env->code = newHInstrSB();

/* Copy BB's type env. */
/* TODO-JIT: Currently works only with no if-then-else statements. */

Modified: branches/VEX_JIT_HACKS/priv/main_main.c
==============================================================================
--- branches/VEX_JIT_HACKS/priv/main_main.c (original)
+++ branches/VEX_JIT_HACKS/priv/main_main.c Sun Apr 16 21:36:48 2017
@@ -326,12 +326,13 @@
Bool (*isMove) ( const HInstr*, HReg*, HReg* );
void (*getRegUsage) ( HRegUsage*, const HInstr*, Bool );
void (*mapRegs) ( HRegRemap*, HInstr*, Bool );
+ HInstrIfThenElse* (*isIfThenElse)(const HInstr*);
void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool );
void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool );
HInstr* (*directReload) ( HInstr*, HReg, Short );
void (*ppInstr) ( const HInstr*, Bool );
void (*ppReg) ( HReg );
- HInstrArray* (*iselSB) ( const IRSB*, VexArch, const VexArchInfo*,
+ HInstrSB* (*iselSB) ( const IRSB*, VexArch, const VexArchInfo*,
const VexAbiInfo*, Int, Int, Bool, Bool,
Addr );
Int (*emit) ( /*MB_MOD*/Bool*,
@@ -347,9 +348,9 @@

VexGuestLayout* guest_layout;
IRSB* irsb;
- HInstrArray* vcode;
- HInstrArray* rcode;
- Int i, j, k, out_used, guest_sizeB;
+ HInstrSB* vcode;
+ HInstrSB* rcode;
+ Int out_used, guest_sizeB;
Int offB_CMSTART, offB_CMLEN, offB_GUEST_IP, szB_GUEST_IP;
Int offB_HOST_EvC_COUNTER, offB_HOST_EvC_FAILADDR;
UChar insn_bytes[128];
@@ -413,6 +414,7 @@
getRegUsage
= (__typeof__(getRegUsage)) X86FN(getRegUsage_X86Instr);
mapRegs = (__typeof__(mapRegs)) X86FN(mapRegs_X86Instr);
+ isIfThenElse = (__typeof__(isIfThenElse)) X86FN(isIfThenElse_X86Instr);
genSpill = (__typeof__(genSpill)) X86FN(genSpill_X86);
genReload = (__typeof__(genReload)) X86FN(genReload_X86);
directReload = (__typeof__(directReload)) X86FN(directReload_X86);
@@ -878,7 +880,7 @@

vassert(vta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3);
vassert(vta->guest_extents->base[0] == vta->guest_bytes_addr);
- for (i = 0; i < vta->guest_extents->n_used; i++) {
+ for (UInt i = 0; i < vta->guest_extents->n_used; i++) {
vassert(vta->guest_extents->len[i] < 10000); /* sanity */
}

@@ -897,7 +899,7 @@
UInt guest_bytes_read = (UInt)vta->guest_extents->len[0];
vex_printf("GuestBytes %lx %u ", vta->guest_bytes_addr,
guest_bytes_read );
- for (i = 0; i < guest_bytes_read; i++) {
+ for (UInt i = 0; i < guest_bytes_read; i++) {
UInt b = (UInt)p[i];
vex_printf(" %02x", b );
sum = (sum << 1) ^ b;
@@ -1042,17 +1044,13 @@
vex_printf("\n");

if (vex_traceflags & VEX_TRACE_VCODE) {
- for (i = 0; i < vcode->arr_used; i++) {
- vex_printf("%3d ", i);
- ppInstr(vcode->arr[i], mode64);
- vex_printf("\n");
- }
+ ppHInstrSB(vcode, isIfThenElse, ppInstr, mode64);
vex_printf("\n");
}

/* Register allocate. */
rcode = doRegisterAllocation ( vcode, rRegUniv,
- isMove, getRegUsage, mapRegs,
+ isMove, getRegUsage, mapRegs, isIfThenElse,
genSpill, genReload, directReload,
guest_sizeB,
ppInstr, ppReg, mode64 );
@@ -1063,11 +1061,7 @@
vex_printf("\n------------------------"
" Register-allocated code "
"------------------------\n\n");
- for (i = 0; i < rcode->arr_used; i++) {
- vex_printf("%3d ", i);
- ppInstr(rcode->arr[i], mode64);
- vex_printf("\n");
- }
+ ppHInstrSB(rcode, isIfThenElse, ppInstr, mode64);
vex_printf("\n");
}

@@ -1086,22 +1080,25 @@
}

out_used = 0; /* tracks along the host_bytes array */
- for (i = 0; i < rcode->arr_used; i++) {
- HInstr* hi = rcode->arr[i];
+ /* TODO-JIT: This needs another interface when assembler/flattener
+ is given whole HInstrSB and also pointer to function
+ which prints emitted bytes. */
+ for (UInt i = 0; i < rcode->insns->insns_used; i++) {
+ HInstr* hi = rcode->insns->insns[i];
Bool hi_isProfInc = False;
if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
ppInstr(hi, mode64);
vex_printf("\n");
}
- j = emit( &hi_isProfInc,
- insn_bytes, sizeof insn_bytes, hi,
- mode64, vta->archinfo_host.endness,
- vta->disp_cp_chain_me_to_slowEP,
- vta->disp_cp_chain_me_to_fastEP,
- vta->disp_cp_xindir,
- vta->disp_cp_xassisted );
+ Int j = emit(&hi_isProfInc,
+ insn_bytes, sizeof insn_bytes, hi,
+ mode64, vta->archinfo_host.endness,
+ vta->disp_cp_chain_me_to_slowEP,
+ vta->disp_cp_chain_me_to_fastEP,
+ vta->disp_cp_xindir,
+ vta->disp_cp_xassisted);
if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) {
- for (k = 0; k < j; k++)
+ for (Int k = 0; k < j; k++)
vex_printf("%02x ", (UInt)insn_bytes[k]);
vex_printf("\n\n");
}
@@ -1118,7 +1115,7 @@
res.offs_profInc = out_used;
}
{ UChar* dst = &vta->host_bytes[out_used];
- for (k = 0; k < j; k++) {
+ for (Int k = 0; k < j; k++) {
dst[k] = insn_bytes[k];
}
out_used += j;
@@ -1132,8 +1129,8 @@

if (vex_traceflags) {
/* Print the expansion ratio for this SB. */
- j = 0; /* total guest bytes */
- for (i = 0; i < vta->guest_extents->n_used; i++) {
+ UInt j = 0; /* total guest bytes */
+ for (UInt i = 0; i < vta->guest_extents->n_used; i++) {
j += vta->guest_extents->len[i];
}
if (1) vex_printf("VexExpansionRatio %d %d %d :10\n\n",

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